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65nm Migration Case Studies

WLAN Chip – Multiple Modules: US based division of a European IDM

90nm and 65nm ported WLAN bias circuit90nm and 65nm ported WLAN bias circuit

90nm and 65nm ported WLAN bias circuit

Type of chip/IP:

  • 33 modules including RF blocks with inductors

 

Business Goals:

  • Achieve early availability of WLAN IP (developed at 90nm) in 65nm process node to support other SoC development programs
  • Avoid the need to redesign existing IP or tie up valuable analog/RF design resources
  • Avoid estimated 18 month cycle time to redevelop the same WLAN IP for 65nm

 

Source Process:

  • Crolles/TSMC 90nm RF

 

Target Process:

  • Crolles/TSMC 65nm RF

 

Size of die/IP pre migration:

  • Various

 

Size of die/IP post migration:

  • Various

 

Project Cycle time:

  • 16 calendar weeks for porting of layout and schematics to target process/PDK

 

Results:

  • Silicon success first time
  • Simulation work on extracted layout achieved target specifications

 


ISM Single Chip Radio – Multiple Analog Mixed Signal Modules: US Fabless Vendor

 

Type of chip/IP:

  • Eight ISM single chip radio modules including RF blocks with inductors

 

Business Goals:

  • Achieve aggressive market window to integrate ISM chip IP (developed at 0.18 micron) into an end customer platform chip development at 65nm process node

 

Source Process:

  • TSMC CM018RG

 

Target Process:

  • TSMC CLN65LP

 

Size of die/IP pre migration:

  • Top level 3080um x 3050um

 

Size of die/IP post migration:

  • Confidential

 

Project Cycle time:

  • 14 weeks for porting of layout and schematics to target process/PDK

 

Results:

  • Design completely met target specifications

 


Analog Mixed Signal IP Modules: European IDM

90nm and 65nm ported bandgap section90nm and 65nm ported bandgap section

90nm and 65nm ported bandgap section

Type of chip/IP:

  • 15 analog mixed signal IP modules including ADCs, DACs, PLLs, bandgaps

 

Business Goals:

  • Achieve early availability of qualified analog mixed signal modules used widely across the corporation in 65nm process node to support various SoC development programs
  • Avoid the need to redesign existing IP or tie up valuable analog design resources
  • Avoid estimated 12-15 month cycle time to redevelop the same IP for 65nm

 

Source Process:

  • Crolles/TSMC 90nm

 

Target Process:

  • Crolles/TSMC 2.5V option 65nm

 

Size of die/IP pre migration:

  • Various

 

Size of die/IP post migration:

  • Same

 

Project Cycle time:

  • 16 calendar weeks for porting of layout and schematics to target process/PDK

 

Results:

  • Working first time silicon for all modules
  • Used in SoC designs some of which are in production
  • Same modules have subsequently been migrated to 45nm process node

 

Bluetooth Chip – Multiple Modules: European IDM

 

Type of chip/IP:

  • Various Bluetooth modules including RF blocks with inductors

 

Business Goals:

  • Achieve early availability of Bluetooth IP (developed at 0.18 micron) in 65nm process node to support other SoC developments
  • Avoid the need to redesign existing IP or tie up valuable analog/RF design resources
  • Top level 3080um x 3050um
  • Avoid estimated 15-18 month cycle time to redevelop the same IP for 65nm

 

Source Process:

  • Crolles 0.18 micron RF

 

Target Process:

  • Crolles/TSMC 65nm

 

Size of die/IP pre migration:

  • Various

 

Size of die/IP post migration:

  • Various

 

Project Cycle time:

  • 10 weeks for porting of layout and schematics to target process/PDK

 

Results:

  • Silicon success first time
  • Simulation work on extracted layout achieved target specifications

 


HDMI IP Core: European IDM

90nm and 65nm ported HDMI section90nm and 65nm ported HDMI section

90nm and 65nm ported HDMI section

Type of chip/IP:

  • HDMI module

 

Business Goals:

  • Achieve fast availability of HDMI IP core (developed at 0.18 micron) in 65nm process node to support other SoC developments
  • Avoid the need to redesign existing IP or tie up valuable analog/RF design resources
  • Avoid estimated 12 month cycle time to redevelop the same IP for 65nm

 

Source Process:

  • Crolles/TSMC 0.18 micron

 

Target Process:

  • Crolles/TSMC 65nm LP

 

Size of die/IP pre migration:

  • Confidential

 

Size of die/IP post migration:

  • Confidential

 

Project Cycle time:

  • 8 calendar weeks for porting of layout and schematics to target process/PDK

 

Results:

  • Silicon success first time
  • IP core has been designed into to various SoC projects
  • Same core has subsequently been migrated to 45nm process node

 


GSM Cellular Chip – Multiple Modules: European IDM

 

Type of chip/IP:

  • 17 modules including RF blocks with inductors, Tx, Rx, LNA, mixer, PLLs, VCO

 

Business Goals:

  • Achieve early availability of GSM IP (developed at 90nm) in 65nm process node to support an overall SoC die shrink at 65nm for cost sensitive consumer applications
  • Achieve aggressive market window to enable critical design-wins for business unit
  • Avoid estimated 15-18 month cycle time to redevelop the existing GSM IP in 65nm
  • Free up resources to support new cellular/mobile design work

 

Source Process:

  • Crolles/TSMC 90nm RF

 

Target Process:

  • Crolles/TSMC 65nm RF
 

Project Cycle time:

  • 11 calendar weeks for porting of layout and schematics to target process/PDK

 

Results:

  • Silicon success first time
  • Simulation work on extracted layout achieved target specifications

 


PCI Express IP Core: European IDM

European IDMEuropean IDM

Type of chip/IP:

  • PCI Express Rx and Tx modules containing 13 blocks including SerDes (PHY)

 

Business Goals:

  • Achieve early availability of PCIe core (developed at 90nm) in 65nm process node to support meet urgent customer demand
  • Avoid the need to redesign existing IP or tie up valuable analog/RF design resources
  • Avoid estimated cycle time in excess of 12 month to redevelop the same IP for 65nm

 

Source Process:

  • Crolles/TSMC 90nm

 

Target Process:

  • Crolles/TSMC 2.5V option 65nm

 

Size of die/IP pre migration:

  • Confidential

 

Size of die/IP post migration:

  • Confidential

 

Project Cycle time:

  • 8 calendar weeks for porting of layout and schematics to target process/PDK

 

Results:

  • Silicon successfully qualified for SoC development
  • IP core has been designed into to various SoC projects
  • Same core has subsequently been migrated to 45nm process node

 

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