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OSIRIS Layout Migration


Migrating layout from one process to another is a complex process that combines the translation of physical information with the complexities of translating parameterised cells and other advanced circuit elements. IN2FAB's OSIRIS layout migration tools operate within the Cadence framework, making them 100% compatible with process design kits and technology files that are built for Cadence's Design Framework or OpenAccess tools.


Migration Overview

OSIRIS layout migration tools are designed to simplify the complexities of translating circuit elements between processes and foundries.  Interactive tools identify the elements in each circuit and guide the user through the process of translating them between the original and new design kits.  

Advanced circuit elements such as Pcells and ROD objects are translated and placed in the new circuit straight from the target design kit, ensuring complete compatilbility with the new design environment and verification tools.  

Design migration can be run as a batch process or interactively within the Virtuoso editor, giving engineers the freedom to adjust or modify their design at any time.  Controlled processing options also allows sections of the design hierarchy to be translated, giving users complete control over the migration process.
layout methodology

Component Mapping

OSIRIS migrates all circuit elements and places equivalent objects in the new database.  Pcells are mapped by device type and key properties while other complex elements such as RODs and guard rings are translated to new layers and adjusted to match the requirements of the new process rules.

Property types are converted automatically during the migration process to ensure parameters completely match the requirements of the new PDK.
Physical properties that control the elements of each component can be read from the original layout or set at run time to ensure the requirements of the new process are met.

Optional extra features allow custom or unique Pcells to be translated as instances to the new process layers to maintain circuit integrity.


Capabilities and Features

OSIRIS layou migration features a host of features and capabilities to process even the most complex layout structures.  Maps of layers, vias and Pcells are fully GUI driven to guide the user through the process of transferring circuit elements from one process to another.

OSIRIS processes advanced circuit elements with ease including Pcells, ROD objects and fluid guard rings, transferring them to the new database while maintaining them as fully editable design objects.  Netlist information and design constraints are also migrated giving matching Virtuoso XL functionality in the migrated circuit.




Alignment and Connection

Differences between the source and target process rules often mean that component must be adjusted to maintain aligment and connectivity.  Changes in rules such as contact to gate spacing can mean components are separated from overlapping cells and from routing shapes.

OSIRIS recognises component alignment in the circuits and makes small adjustments to the placement and routing in the migrated circuit to align and reconnect components. Connections through contact overlap or wire and polygon interconnect are automatically resloved as each circuit is migrated.
 

Post-migration Adjustment

OSIRIS features a host of interactive layout adjustment tools that allow users to make further updates to circuit layouts and resolve critical rules or layout requirements.

Shapes and layers can be adjusted to meet new DRC rules or to update circuit elements locally or through the whole circuit. Interactive circuit changes can also be made using the Virtuoso editor to resolve final layout issues and complete the migration process.

 

Copyright IN2FAB Technology 2014