OSIRIS's mapping, placement and re-wiring capabilities take it far beyond the functionality of a simple component swapper. Interactive GUIs find circuit symbols in the source design and guide the mapping of pins and parameters to the target symbol and reference libraries such as standard cells can be replaced with versions from the new foundry.
Physical differences between PDKs such as cell origin, symbol size or pin differences are automatically resolved. Rewiring tools allow new pins to be added and tied to specified nets while stray wires from deleted pins are cleaned from the circuit. Component checking and re-wiring ensures that full circuit hierarchies are migrated in a single pass.
The complexities of property translation between source and target PDKs are handled automatically without users needing to convert between types. Optional recalculation can be invoked to adjust physical parametes to retain passive values.
|Pin and Parameter Mapping
The task of mapping pins and parameters between PDKs is controlled through the OSIRIS graphical interfaces. Information from the original and new PDKs are identified and presented to the user in a clear format for easy mapping and conversion. Values can be modified by simple scaling or through complex relationships as required.
Pins are automatically rerouted to ensure connectivity even when symbols and pin positions differ and shorts caused by new pin locations are automatically identified and resolved.
Intelligent parameter assignment and callback triggers allow even the most complex components to be converted for simulation or layout constraints. Advanced commands also deal with complex demands and component modifications to resolve difficult constraints in the target process.
OSIRIS schematic migration features a host of features and capabilities that make it the most powerful and versatile schematic migration tool available. From legacy processes through to the most advanced nanometer and FinFET designs, OSIRIS tools can migrate the most complex designs between processes from independent manufacturers and custom foundries.
Advanced features of the schematic databases such as hierarchical parameters and netset properties are fully retained to deliver a completely migrated schematic which contains the full functionality of the original design.
API level extensions allow the flow to be customized to meet the demands of the most complex migration requirements. From transistor adjustments to complex passive calculations, OSIRIS has been used to solve the most difficult mapping and translation challenges to rapidly move IP to new foundries and processes.
Checking that the migrated schematic maintains the integrity of the circuit while following the intent of the migration is an essential part of circuit migration. OSIRIS features a dedicated migration comparison tool that check the placement, connectivity and parameters of the target circuit to ensure it matches the original.
Unlike an LVS tool, schematic comparison accounts for differences in component names, parameter types and values to instantly identify discrepancies between old and new circuits. Problems such as max/min size violations or component crowding are reported and highlighted within the schematic editor for easy identification and resolution.