Migration to SOI

Global Foundries has invested heavily in new technologies including a range of Silicon on Insulator (SOI) processes for advanced SoCs. This process is ideal for devices that must combine high performance with extremely low power consumption but without the high cost of FinFET manufacturing. 

Migrating circuits to an SOI process presents extra challenges that are not found in bulk silicon technology.  Devices can adjusted to take advantage of the benefits of body biasing and other factors like layer coloring, dummy shapes and layout dependent effects as well as complex changes in device construction and rules must also be addressed. 

Migration from planar technology to SOI preserves the hierarchy and topology of the original circuit while adjusting the components to suit the new technology.  

Schematic and layout data are translated through map files that describe the old and new circuit elements along with pin and parameter information.  Core circuit components will be replaced with equivalent devices from the new PDK and any standard cells placed in the analog hierarchy should also be swapped to elements from a library in the new process. 

Parameter limits play an important part in process migration and tools must recognise instances that must change in the target process due to limits in maximum or minimum values and adapt them accordingly.  Similar changes are often required in passive components where new sizes or number of segments are required.  OSIRIS migration tools calculate the values automatically so there is no need for engineers to calculate conversion factors.

Once the schematic migration is complete and the test benches are converted, the circuit can run through first level simulation.  This should confirm overall functionality of the system in the new process as the simulation is using models from the 22FDX® libraries.

A migrated schematic means that designers can get to the circuit tuning level without having to worry about building an entirely new design from scratch.  Once this migration flow is configured, even large designs can be migrated and ready for simulation in a matter of hours.

Layout migration is much more complex than translating schematics and moving from bulk silicon to an SOI process presents some extra challenges.  However, a comprehensive migration flow will address the intricacies of the different circuit elements while giving designers control and flexibility to update the circuits where necessary.  While schematic migration is fully automated, some sort of interaction is usually necessary during layout migration to adapt the design where necessary.

The key to migrating analog layout is to use foundry elements from the target PDK to build the migrated design.  Parameterised cells (Pcells), vias and shape based data from the original circuit are replaced by elements from the new PDK through the hierarchy with component parameters adapted as required.  A shape based flow that reduces the design to a collection of polygons will never be able to convert bulk silicon layout to SOI but using Pcells means that devices are correct by construction wherever they are placed.  The parameters for active components are adapted to match the original while passives can retain their value while physical dimensions are updated to give the correct values in the new process.

IN2FAB’s design migration technology has been used to move hundreds of circuits between foundries and process nodes.  OSIRIS migration brings major benefits when moving planar circuits to 22FDX® and beyond.