Translating External Schematic Databases to Cadence Virtuoso

Many vendors have moved to Si2’s OpenAccess platform, but a range of tools are based on other formats.  Some of these tools are supported by larger companies, including Analog Devices’ LTSpice, Google/Skywater’s XSCHEM and SLED from Dolphin Design.  

In addition, many circuits have been created and archived using older tools such as Viewlogic, where licenses may not even be available to open the circuits for editing or review.

IN2FAB’s circuit migration service group sees databases from a wide variety of sources, including proprietary and external tools.  This has led to the development of direct database-level translators which import external data directly to Cadence Virtuoso.  Single and multiple libraries are translated along with PDK level components to reconstruct an entire circuit hierarchy in a single pass.  Symbol and schematic design directories and files are read directly and output in Cadence Virtuoso format.  

Circuits are converted directly from the file system to give a complete replica of the original design, with a topology and hierarchy that matches the original.  Properties are attached to core circuit elements and the design can viewed, edited in Virtuoso and also used to create a netlist. 

However, it is usually much more useful to further process the data to use elements from a foundry PDK in Cadence format.   This can be achieved using the OSIRIS Schematic Migration tools which are dedicated to moving schematics between a wide variety of PDKs and process nodes.

Translating a schematic to a new PDK involves addressing physical and property level issues.  Most imported schematics need to be scaled down to match the size of the Cadence PDK and wires and pins must be snapped to a fixed grid to ensure connections are maintained.  Symbols may also have different origin points and orientation so this must also be considered through the translation process.  

The tools that move the schematics to the Cadence PDK must be able to reconnect wires that have become detached from pins to maintain circuit connectivity.  They must also trim back any wires that overshoot a pin to prevent the Check & Save function from flagging wires with a hanging connection. 

Automatic rewiring routines in the OSIRIS migration suite address differences between old and new pins and adjust wires to new positions.  They also identify short circuits caused by differences in symbol pin positions and move wires to route around the problem.

Property translation must also be completed, and this can be a surprisingly difficult part of the process. Device parameters must be adapted to new formats and trigger callbacks to set values for simulation properties.  Parameter formats can vary between technologies, and the OSIRIS migration tools will adapt parameter values and types to any PDK format.