Standard Cell Library Reuse

Migrating the schematics is reasonably straightforward as the cells will use a limited number of symbols, usually N and P transistors and antenna diodes.  It may be possible to complete the task with an instance swapping script, although this may be complicated by restrictions in properties and callbacks.  A fully featured schematic migrator can deal with those during the migration process, or they can be fixed by further enhancing the script.  

Engineers can adjust gate sizes to suit the new process.  Gate lengths can be set to the target rules and widths adjusted to in proportion or by some other formula.   More complicated adjustment may be needed for FinFET technology but this can all be programmed in to the migration flow.

Layout migration is always much harder than translating schematics, although standard cells contain simple polygon-based devices.  Most of the layers will have a 1:1 map to the new technology but that’s where the similarities often end.  Changes in design rules will affect almost every shape in the cells and they may also have to adapt to new cell height and routing grid rules.  

Migration of standard cells or memories can be greatly accelerated using tools called compactors.  These compile the design rules into a special command file which is then applied to the layers in the cells.  However, setting up these tools proved extremely difficult which limited their use, and some of the best-known compactors, such as Sagantec’s Dream, are no longer available. 

The OSIRIS Standard Cell option automatically retrieves the design rule information from the technology file and compiles it into  control files for Cadence’s VLM compaction engine.  OSIRIS also adds special control structures to each cell and this is applied to an entire standard cell library in a single pass.  Global information such as cell height, power rails, pin grids and layer alignment are also included in the control files to ensure routing compliance.

OSIRIS can also be used to change the routing pitch for existing cell libraries to deliver extra layout density.  Users can set the routing pitch for X and Y the library is processed through the compactor to adjust metal and pin positions to meet the new rules.  Experimental metal pitches can be evaluated simply by changing the spacing values to deliver accurate results across entire libraries.

Once the migration is complete, OSIRIS automatically generates test structures to ensure the contents and periphery of each cell complies with the new design rules.  Standard DRC & LVS can be run on the entire library in a single pass and extra rules or constraints can be added to the control file if necessary.  The control files mean the library can be reprocessed in a matter of seconds to accommodate any extra rules or constraints.  

Rapid standard cell migration can enable new digital products across a range of foundries and manufacturing processes.  The OSIRIS standard cell option delivers entire libraries in a matter of minutes to enable true process flexibility.